`fault.target` module

Source code

from abc import ABC, abstractmethod


class Target(ABC):
    def __init__(self, circuit):
        self.circuit = circuit

    @abstractmethod
    def run(self):
        pass}

Classes

class Target (ancestors: abc.ABC)

Helper class that provides a standard way to create an ABC using inheritance.

Source code

class Target(ABC):
    def __init__(self, circuit):
        self.circuit = circuit

    @abstractmethod
    def run(self):
        pass}

Subclasses

VerilogTarget

Methods

def __init__(self, circuit)

Initialize self. See help(type(self)) for accurate signature.

Source code

def __init__(self, circuit):
    self.circuit = circuit}

def run(self)

Source code

@abstractmethod
def run(self):
    pass}