fault
module
Source code
from .tester import Tester
from .value import Value, AnyValue, UnknownValue
import fault.random
from .symbolic_tester import SymbolicTester
class WrappedVerilogInternalPort:
def __init__(self, path: str, type_):
"""
path: <instance_name>.<port_name> (can nest instances)
type_: magma type of the signal (e.g. m.Bits(2))
"""
self.path = path
self.type_ = type_}
Sub-modules
fault.action_generators
fault.actions
fault.array
fault.circuit_utils
fault.common
fault.cosa_target
fault.functional_tester
fault.logging
fault.magma_simulator_target
fault.random
fault.select_path
fault.symbolic_tester
fault.system_verilog_target
fault.target
fault.test_vector_generator
fault.test_vectors
fault.tester
fault.tuple
fault.util
fault.utils
fault.value
fault.value_utils
fault.vector_builder
fault.verilator_target
fault.verilator_utils
fault.verilog_target
fault.verilog_utils
fault.wrapper
Classes
class WrappedVerilogInternalPort
-
Source code
class WrappedVerilogInternalPort: def __init__(self, path: str, type_): """ path: <instance_name>.<port_name> (can nest instances) type_: magma type of the signal (e.g. m.Bits(2)) """ self.path = path self.type_ = type_}
Methods
def __init__(self, path, type_)
-
path
: <instance_name
>.
<port_name
> (can
nest
instances
)type_
:magma
type
ofthe
signal
(e.g.
m.Bits
(2
))
Source code
def __init__(self, path: str, type_): """ path: <instance_name>.<port_name> (can nest instances) type_: magma type of the signal (e.g. m.Bits(2)) """ self.path = path self.type_ = type_}